1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of electric circuits having the same configuration, which are mounted on the same semiconductor chip. The invention also pertains to a test method of the device.
2. Description of the Related Art
When a plurality of electric circuits having the same configuration are formed on one LSI chip, it is desired that these circuits having the same configuration is effectively tested in the manufacturing process. For example, it is recently required to perform a high-speed data transfer between LSI chips, boards or chassis. In a signal receiving circuit including a clock recovery circuit used for correctly performing such a signal reception between LSI chips, a plurality of circuits having the same configuration are usually mounted on the same chip according to the number of signals to be transmitted between the LSI chips.
FIG. 8 shows a schematic configuration of a digital filter and a test circuit thereof provided on a conventional signal receiving circuit.
On an LSI chip 500 shown in FIG. 8, a digital filter 510 is provided as a part of a signal receiving circuit. A plurality of the filters 510 having the same configuration are mounted on the LSI chip 500 according to the number of receiving channels of the signals.
As shown in FIG. 8, the digital filter 510 has a Phase to Digital Converter (PDC) 511 that receives signals from an internal circuit of the LSI chip 500, a register 512, and an addition circuit 513 that adds respective outputs of the PDC 511 and the register 512 and feeds back the result to the register 512. In this digital filter 510, an integration circuit is configured by the register 512 and the addition circuit 513.
Conventionally, an operation test of this digital filter 510 is carried out as follows. A BIST (Built-In Self Test) controller 520 used for realizing a BIST is previously provided on the LSI chip 500. From the BIST controller 520, a control signal is imparted to the PDC 511 to allow the PDC 511 to act as an output circuit of a test pattern. At this time, the integration circuit including the register 512 and the addition circuit 513 is operated as a test target circuit. Concretely, an output value of the PDC 511 is set, for example, to a fixed value of “1” by the control of the BIST controller 520. At this time, the integration circuit including the register 512 and the addition circuit 513 executes an increment operation by “plus one”. Then, an output value of the integration circuit is inputted to a comparison circuit 600 outside the LSI chip 500 and compared with an expected value of a test pattern, whereby it can be determined whether the digital filter 510 is correctly operated.
For a conventional related art, a system is disclosed in which a plurality of controlled devices are daisy-chained to a controller by cables. In the system, four signal lines are newly added to existing signal lines. Termination setting state check circuits having the same configuration, which are connected by these four signal lines, are mounted within the respective controlled devices. When an ID of the controlled device is designated from the controller through three signal lines among the above-described signal lines, a response signal is fed back from any one of the termination setting state check circuits through the other signal line, whereby a control disabling factor can be specified. See, e.g., Japanese Unexamined Patent Publication No. Hei 9-218735, paragraph numbers [0008] to [0013] and FIG. 2.
In the above-described test method shown in FIG. 8, a test must be performed for each unit of a signal receiving circuit and therefore, as the number of receiving channels is larger, a test time is more increased. In addition, since an exterior comparison circuit 600 is used, a lot of trouble of connecting a device is taken in performing a test for all the units. Further, expected values of a test pattern for the comparison by the comparison circuit 600 must be prepared separately, and moreover, the expected values must be prepared as many as the number of units.